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IDT74FCT163501A/C 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 18-BIT REGISTERED TRANSCEIVER
IDT74FCT163501A/C
* 0.5 MICRON CMOS Technology * Typical tSK(o) (Output Skew) < 250ps * ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) * VCC = 3.3V 0.3V, Normal Range, or VCC = 2.7V to 3.6V, Extended Range * CMOS power levels (0.4 W typ. static) * Rail-to-rail output swing for increased noise margin * Low Ground Bounce (0.3V typ.) * Inputs (except I/O) can be driven by 3.3V or 5V components * Available in SSOP, TSSOP, and TVSOP packages
FEATURES:
DESCRIPTION:
The FCT163501 18-bit registered transceivers are built using advanced dual metal CMOS technology. These high-speed, low-power 18-bit registered bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch enable (LEAB and LEBA) and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A bus data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. OEAB performs the output enable function on the B port. Data flow from B port to A port is similiar but requires using OEBA, LEBA and CLKBA. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. The FCT163501 has series current limiting resistors. These offer low ground bounce, minimal undershoot, and controlled output fall timesreducing the need for external series terminating resistors.
FUNCTIONAL BLOCK DIAGRAM
OEAB CLKBA LEBA OEBA CLKAB LEAB
1
30
28
27
55
2
C A1
3
C D
54
D
B1
C D
C D
TO 17 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
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(c) 2002 Integrated Device Technology, Inc.
APRIL 2002
DSC-2776/6
IDT74FCT163501A/C 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
OEAB LEAB A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA LEBA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 GND CLKAB B1 GND B2 B3 VCC B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VCC B16 B17 GND B18 CLKBA GND
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM(2) VTERM(3) VTERM(4) TSTG IOUT Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Max -0.5 to +4.6 -0.5 to 7 -0.5 to VCC+0.5 -65 to +150 -60 to +60 Unit V V V C mA
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Vcc terminals. 3. Input terminals. 4. Outputs and I/O terminals.
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 3.5 3.5 Max. 6 8 Unit pF pF
NOTE: 1. This parameter is measured at characterization but not tested.
FUNCTION TABLE(1,4)
Inputs OEAB L H H H H H H LEAB X H H L L L L CLKAB X X X L H Ax X L H L H X X Outputs Bx Z L H L H B(2) B(3)
SSOP/ TSSOP/ TVSOP TOP VIEW
PIN DESCRIPTION
Pin Names OEAB OEBA LEAB LEBA CLKAB CLKBA Ax Bx Description A-to-B Output Enable Input B-to-A Output Enable Input (Active LOW) A-to-B Latch Enable Input B-to-A Latch Enable Input A-to-B Clock Input B-to-A Clock Input A-to-B Data Inputs or B-to-A 3-State Outputs B-to-A Data Inputs or A-to-B 3-State Outputs
NOTES: 1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA. 2. Output level before the indicated steady-state input conditions were established. 3. Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. 4. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-Impedance = LOW-to-HIGH Transition
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IDT74FCT163501A/C 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40C to +85C, VCC = 2.7V to 3.6V
Symbol VIH VIL IIH IIL IOZH IOZL VIK IODH IODL VOH Parameter Input HIGH Level (Input pins) Input HIGH Level (I/O pins) Input LOW Level (Input and I/O pins) Guaranteed Logic LOW Level Input HIGH Current (Input pins) Input HIGH Current (I/O pins) Input LOW Current (Input pins) Input LOW Current (I/O pins) High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Output HIGH Current Output LOW Current Output HIGH Voltage VCC = Min., IIN = -18mA VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V VCC = Min. VIN = VIH or VIL VCC = 3V VIN = VIH or VIL VOL Output LOW Voltage VCC = Min. VIN = VIH or VIL VCC = 3V VIN = VIH or VIL IOS VH ICCL ICCH ICCZ Short Circuit Current Input Hysteresis Quiescent Power Supply Current VCC = Max. VIN = GND or VCC
(4) (3) (3)
Test Conditions(1) Guaranteed Logic HIGH Level
Min. 2 2 -0.5
Typ.(2) -- -- -- -- -- -- -- -- -- -0.7 -60 90 -- 3 3 -- 0.2 0.3 0.3 -135 150 0.1
Max. 5.5 VCC+0.5 0.8 1 1 1 1 1 1 -1.2 -110 200 -- -- -- 0.2 0.4 0.55 0.5 -240 -- 10
Unit V V A
VCC = Max.
VI = 5.5V VI = VCC VI = GND VI = GND
-- -- -- -- -- -- -- -36 50 VCC-0.2 2.4 2.4
(5)
VCC = Max.
VO = VCC VO = GND
A
V mA mA V
IOH = -0.1mA IOH = -3mA IOH = -8mA IOL = 0.1mA IOL = 16mA IOL = 24mA IOL = 24mA
-- -- -- -- -60
V
VCC = Max., VO = GND(3) --
mA mV A
-- --
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25C ambient. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. VOH = VCC-0.6V at rated current.
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IDT74FCT163501A/C 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) VCC = Max. VIN = VCC - 0.6V(3) VCC = Max. Outputs Open OEAB = OEBA = VCC or GND One Input Togging 50% Duty Cycle VCC = Max.,Outputs Open fCP = 10MHz (xCLKAB) 50% Duty Cycle OEAB = OEBA = VCC LEAB = GND fI = 5MHz 50% Duty Cycle One Bit Toggling VCC = Max.,Outputs Open fCP = 10MHz (xCLKAB) 50% Duty Cycle OEAB = OEBA = VCC LEAB = GND fI = 2.5MHz 50% Duty Cycle Eighteen Bits Toggling
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25C ambient. 3. Per TTL driven input. All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fi = Input Frequency Ni = Number of Inputs at fi
Test Conditions(1)
Min. --
Typ.(2) 2 60
Max. 30 100
Unit A A/ MHz
VIN = VCC VIN = GND
--
IC
Total Power Supply Current(6)
VIN = VCC VIN = GND
--
0.6
1
mA
VIN = VCC - 0.6V VIN = GND VIN = VCC VIN = GND
--
0.6
1
--
3
5(5)
VIN = VCC - 0.6V VIN = GND
--
3
5.3(5)
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IDT74FCT163501A/C 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE(1)
Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tSU tH tW tW tSK(o) Parameter CLKAB or CLKBA frequency Propagation Delay Ax to Bx or Bx to Ax Propagation Delay LEBA to Ax, LEAB to Bx Propagation Delay CLKBA to Ax, CLKAB to Bx Output Enable Time OEBA to Ax, OEAB to Bx Output Disable Time OEBA to Ax, OEAB to Bx Set-up Time HIGH or LOW Ax to CLKAB, Bx to CLKBA Hold Time HIGH or LOW Ax to CLKAB, Bx to CLKBA Set-up Time HIGH or LOW Clock LOW Ax to LEAB, Bx to LEBA Clock HIGH Hold Time HIGH or LOW Ax to LEAB, Bx to LEBA LEAB or LEBA Pulse Width HIGH(4) CLKAB or CLKBA Pulse Width HIGH or LOW(4) Output Skew(5) Condition(2) CL = 50pF RL = 500 FCT163501A Min.(3) Max. -- 150 1.5 5.1 1.5 1.5 1.5 1.5 3 0 3 1.5 1.5 3 3 -- 5.6 5.6 6 5.6 -- -- -- -- -- -- -- 0.5 FCT163501C Min.(3) Max. -- 150 1.5 4.6 1.5 1.5 1.5 1.5 3 0 3 1.5 1.5 3 3 -- 5.3 5.3 5.6 5.2 -- -- -- -- -- -- -- 0.5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 1. Propagation Delays and Enable/Disable times are with VCC = 3.3V 0.3V, Normal Range. For VCC = 2.7V to 3.6V, Extended Range, all Propagation Delays and Enable/Disable times should be degraded by 20%. 2. See test circuit and waveforms. 3. Minimum limits are guaranteed but not tested on Propagation Delays. 4. This parameter is guaranteed but not tested. 5. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
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IDT74FCT163501A/C 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
V CC 500 VIN Pulse Generator RT D.U.T. 50pF CL 500 VOUT 6v Open GND
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch 6V GND Open
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test Circuits for All Outputs
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC.
tSU
tH
tREM
3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
1.5V
1.5V
tSU
tH
Pulse Width
Set-up, Hold, and Release Times
ENABLE SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL 3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V CONTROL INPUT tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH 6V tPZH SWITCH GND 3V 1.5V tPHZ 0.3V 1.5V 0V 0V VOH tPLZ DISABLE 3V 1.5V 0V 3V 0.3V VOL
Propagation Delay
Enable and Disable Times
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns. 3. if VCC is below 3V, input voltage swings should be adjusted not to exceed VCC.
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IDT74FCT163501A/C 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XX FCT XXX Temp. Range Family XXXX X Device Type Package
PV PA PF 501A 501C 163 74
Shrink Small Outline Package Thin Shrink Small Outline Package Thin Very Small Outline Package Non-Inverting 18-Bit Registered Transceiver
Double-Density 3.3Volt - 40C to +85C
DATA SHEET DOCUMENT HISTORY
4/22/2002 Removed blank speed grade
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